The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device(hereinbelow referred to as "BiCMOS") which bipolar transistor and complemental metal oxide transistor are formed on the same substrate.
Generally, a small component system interface ("SCCI") chip is being used in controlling compact disc rom driver or hard disc driver of work station computer, and requests high driving current and fast response time.
So as to satisfy such conditions for the SCCI chip, a BiCMOS was provided, in which a complement metal oxide semiconductor ("CMOS") transistor and a bipolar transistor are formed on one semiconductor substrate. The BiCMOS has both advantages. One is a comparatively low electric power consumption which is an advantage of CMOS transistor and the other is a comparatively fast response time which is an advantage of bipolar transistor. As the bipolar transistor for BiCMOS, NPN transistor is mainly used.
Hereinbelow, a conventional method for manufacturing a BiCMOS will be described with reference to the accompanying drawings.
Referring to FIG. 1A, field oxide layer 31 for device isolation is formed at selected portions of a semiconductor substrate 30 with P-typed conductivity by a general local oxidation ("LOCOS") method, and a plurality of active regions displaced between the field oxide layers are defined. Next, so as to prevent damage of the substrate 30 during subsequent ion implantation process, screen oxides 32 are formed on surface of the active regions. In the drawings, a region for the formation of CMOS transistor is referred to as portion "A" and a region for the formation of bipolar transistor is referred to as portion "B". Afterwards, to form collector of bipolar transistor at the portion B, a first mask pattern of photoresist film exposing five active regions, is formed. Thereafter, impurity ions of N-typed conductivity, for example, phosphorous ions are implanted at a given ion implantation energy and at a given dose, thereby to form collector region 34.
Referring to FIG. 1B, after removing the first mask pattern by a widely known plasma ashing process, a second mask pattern 35 is formed. The second mask pattern 35 exposes selected portions of the collector region 34, that is, three active regions bipolar at central portion except both edge active regions. Afterwards, impurity ions of P-typed conductivity, for example, boron ions are implanted into the exposed portion, to thereby form base region 36.
Referring to FIG. 1C, after removing the second mask pattern, a third mask pattern 37 is formed. The third mask pattern 37 exposes either one of two active regions in the portion M. Afterwards, impurity ions of N-typed conductivity, for example, phosphorous ions are implanted into the exposed portion, to thereby form a N-well 38 for PMOS transistor.
Referring to FIG. 1D, after removing the third mask pattern 37, a fourth mask pattern 39 is formed by a conventional photolithography method. The fourth mask pattern 39 exposes a remaining active region of two active regions in the portion B. Afterwards, impurity ions of P-typed conductivity, for example, boron ions are implanted into the exposed portion, to thereby form a P-well 40 for NMOS transistor.
Next, referring to FIG. 1E, after removing the fourth mask pattern 39, the screen oxides 32 are all removed by a widely known method. Thereafter, insulator film such as SiO.sub.2 and conductive film such as polysilicon, are deposited on the resultant substrate in that order, and are then patterned to form gate electrodes 42 and the underlying gate insulating layers 41 on surfaces of the two active region of the portion M.
Afterwards, although not shown in the drawings, a fifth mask pattern for exposing the N-well region 38 and two active regions of the base 36 at both edges, is formed. Impurity ions of P-typed conductivity are then implanted into the exposed portion without the fifth mask pattern, to thereby form source and drain regions 43a and 43b for PMOS transistor, and base region 43c.
Thereafter, after removing the fifth mask pattern(not shown), a sixth mask pattern is formed. The sixth mask pattern exposes the P-well region 40, the outermost two active regions of five active regions within the collector region 34, and the central active region of three active regions within the base region 36. Impurity ions of N-typed conductivity, for example, phosphorous ions, are then implanted into the exposed portion without the sixth mask pattern, to thereby form source and drain regions 44a and 44b for NMOS transistor, collector region 44c, and emitter region 44d.
According to the conventional manufacturing method of BiCMOS described above, it needs six times masking steps in forming the BiCMOS because steps for forming the collector region 44c, the base region 43c, and the emitter region 44d are performed independently from each other. Thus, the conventional method is very complicated, so that yield and throughput for the fabrication of BiCMOS are lowered.